The present invention relates to integrated circuit fabrication using, in part, standard cell corner characterization. More particularly, the present invention provides a method for providing accurate and realistic corner characterization of standard cells utilized in the fabrication of integrated circuits.
In the field of integrated circuit fabrication, it is necessary to design and test the integrated circuit before any production of the integrated circuit is initiated. Until recently, that process required the designers to physically build the integrated circuit and install that circuit into the device with which the circuit was to interact. By requiring the physical fabrication and installation, this process was a slow, laborious, and expensive method of testing the integrated circuit""s functionality.
Fortunately, advances in computer technology and developments in related software now provide the tools which enable a designer to design integrated circuits and to test those circuits using software equivalents or models of that particular circuit. A circuit, in part, is a collection of elements such as, e.g., AND gates, flip-flops, mux""s (multiplexers), and slightly larger XOR and XAND gates. These elements, in turn, contain the transistors that comprise the design.
In an IC (integrated circuit) design, for example, those design circuits commonly consist of millions of transistors, and as such it is difficult to represent those millions of transistors as separate entities. Therefore, to alleviate the lengthy process of separately testing the elements within the design of the circuit, the IC industry has created software standard cell libraries. Standard cell libraries contain the many different standard cells which are utilized in the design of the circuits. A standard cell is a computer and software representation or model of a particular element or component of the circuit being designed. Each standard cell in the standard cell library is characterized by an abstraction. The abstraction is a behavioral description of the timing data of that cell. Circuit abstractions are used by software simulator tools for measuring circuit behavior, such as timing, etc.
ASIC (application specific integrated circuit) design methodology, for example, uses cells from one or more standard cell libraries as building blocks. Each cell in the library has a set of representations corresponding to the functionality, timing, and layout abstraction for the cell. In a synchronous design style supported by ASIC design methodology, successful timing operation of the design can be insured for all timing variations if, during simulation, the design works for, what the industry has termed, the worst-case timing scenario and the best-case timing scenario for the constituting cells. As such, a timing representation of the cell is required to contain at least the worst-case and best-case delay values for an input/inout and output/inout path of the cell. This enables a verification of the design operation for the worst-case and the best-case timing for the cells in a design.
The prevailing standard in the industry is to obtain, with regard to circuit verification, the worst-case and best-case timing values for the worst-case PVT (process, voltage, temperature) corner and the best-case PVT corner. In effect, circuit performance varies based on variations in the process, voltage and temperature of the circuit. In one example, current methodologies accomplish this by averaging the data with regard to PVT in a best-case and a worst-case scenario, and inserting those figures into the abstraction to obtain the necessary timing value scenarios. As such, because the abstraction is based on averages, the best-case scenario is not necessarily the actual best-case and the worst-case scenario is not necessarily the actual worst-case scenario.
In addition, this prevailing industry standard for circuit modelling does not take into account standard cell abstraction variations. Included in the abstraction variations not taken into account, in addition to the actual worst and best case PVT corners, are cross-coupling-within-the-cell variations, over-the-cell-routing-coupling variations, pin-input-capacitance-variations and the associated delay-variation-due-to-near-simultaneous-input-switching variations, and setup-hold-delay variations regarding sequential cells.
With regard to cross-coupling-within-the-cell variations, current methodologies utilize a K-factor for the cross coupling that is considered to be between the possible values of 1.0 and 2.0. Since this is neither the best or worst case scenario, the extractions based upon these numbers will not be the best or worst case scenario.
With regard to over-the-cell-routing-coupling variations, the capacitive loading due to over the cell routing is, in current methodologies, either not accounted for or is reflected as maximum routing for both worst and best case timing. Even when maximum over the routing is accounted for, the K-factor is taken to be an average value between 1.0 and 2.0. As such, since an average is utilized, the best and worst case timing scenarios are not the actual best and worst case scenarios.
With regard to pin-input-capacitance-variations and the associated delay-variation-due-to-near-simultaneous-switching, the input capacitance of an input/inout pin of the cell varies with the direction and the slope of the transition on the pin. The current methodology captures the input capacitance as an average value. Additionally, cell timing can vary in response to the transition direction on other signals. Also affecting cell timing is the temporal proximity of the those transitions. The current methodology accounts for delays caused by single input transitions only for both the worst and best case timing. Because multiple input transitions are not addressed, the best and worst case timing scenarios are not the actual best and worst case scenarios.
With regard to the setup-hold-delay variations regarding sequential cells, the delay through sequential cells varies inversely with the time for which the data has been setup before the clock. The current methodology does not account for this variation.
The prevailing industry standard for circuit modelling does not account for these non-PVT abstractions and therefore does not reflect the real worst-possible-case and best-possible-case timing values. This means that a design verified to work for the worst-case and the best-case as obtained by the current industry standard methodologies can still result in failures in silicon.
Therefore, a need exists for a method of corner characterization of standard cells that provides a model that offers a more accurate and realistic corner characterization. Another need exists for a method that includes an accurate best-case timing scenario in the corner characterization of the standard cell. A further need exists for a method that includes an accurate worst-case timing scenario in the corner characterization of the standard cell.
Thus a need exists for a circuit cell model that achieves improved corner characterization of standard cells. Another need exists for a circuit cell model that fills the above need and which takes into account abstraction variables that are currently not being included in the characterization. A further need exists for a circuit cell model that fills the above needs and which includes an accurate best-case timing scenario in the corner characterization of the standard cell. An additional need exists for a circuit cell model that fills the above needs and which includes an accurate worst-case timing scenario in the corner characterization of the standard cell. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
Accordingly, the present invention provides a memory resident circuit cell model for improved corner characterization of standard cells. The present invention further provides a memory resident circuit cell model that achieves the above listed advantages, and which accounts for timing variations not previously taken into account. Further, the present invention also provides a memory resident circuit cell model method which achieves the above advantages, and which further includes an accurate best-case timing scenario in the corner characterization of the standard cell. Additionally, the present invention provides a memory resident circuit cell model which achieves the above advantages, and which further includes an accurate worst-case timing scenario in the corner characterization of the standard cell.
More specifically, the present invention provides a memory resident circuit cell model for characterizing an integrated circuit cell. The present invention comprises a first aggregate value representing a best case corner and a second aggregate value representing a worst case corner. In the present embodiment, the first and second aggregate value comprise a first delay representation accounting for timing variations of the cell relative to cross-coupling within the cell and a second delay representation accounting for timing variations of the cell relative to over-the-cell-routing-coupling. The first and second aggregate value further comprise a third delay representation accounting for timing variations of the cell for pin-input-capacitance and a fourth delay representation accounting for timing variations of the cell relative to delays due to near simultaneous input switching. The first and second aggregate value further comprise a fifth delay representation accounting for timing variations of the cell relative to interdependent set up, hold, delay variations for sequential cells.
As a result of the above considerations, embodiments of the present invention provide accurate and realistic circuit models that can be used for improved circuit simulation and behavior analysis. When applied to standard cell libraries, the present invention enables more realistic modelling and characterization of the standard cells in a library, thereby reducing the probability of errors in silicon for design using standard cell based methodologies.